G. Jiang, J. Wu, Y. Wang, Y. Ha, J. Sun. “Reconfiguring Three-dimensional Processor Arrays for Fault-tolerance: Hardness and Heuristic Algorithms.”
- Release time:2020-09-16
- Hits:
DOI number:
10.1109/TC.2015.2389846
Journal:
IEEE Transactions on Computers
Key Words:
Logic arrays , Three-dimensional displays , Parallel processing , Fault tolerance , Fault tolerant systems , Indexes , Circuit faults
Note:
CCF A类
Indexed by:
Journal paper
Document Type:
J
Volume:
64
Issue:
10
Page Number:
2926-2939
Translation or Not:
no
Date of Publication:
2015-01-08
Included Journals:
SCI
Links to published journals:
https://ieeexplore.ieee.org/document/7004861