Preprocessing and Partial Re-Routing Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays
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发表刊物：IEEE Transactions on Very Large Scale Integration Systems
关键字：Acceleration,Degradation,Very large scale integration,Logic arrays,Switches,Routing,Fault tolerance,Fault tolerant systems,Redundancy,Heuristic algorithms
摘要：This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from O ((1-¿)·ß· m · n ) to its lower bound O ((1-¿)· m · n ) for m × n host arrays with small fault density ¿, where ß is the expected routing length required per logical column.
论文类型：期刊论文
文献类型：J
卷号：18
期号：2
页面范围：315-319
是否译文：否
发表时间：2012-02-01